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DATA SHEET
TDA8357J Full bridge vertical deflection output circuit in LVDMOS
Product specification Supersedes data of 1999 Nov 10 2002 May 06
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
FEATURES * Few external components required * High efficiency fully DC coupled vertical bridge output circuit * Vertical flyback switch with short rise and fall times * Built-in guard circuit * Thermal protection circuit * Improved EMC performance due to differential inputs. GENERAL DESCRIPTION
TDA8357J
The TDA8357J is a power circuit for use in 90 and 110 colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown.
QUICK REFERENCE DATA SYMBOL Supplies VP VFB Iq(P)(av) Iq(FB)(av) Ptot Vi(p-p) Io(p-p) Flyback switch Io(peak) Tstg Tamb Tj maximum (peak) output current t 1.5 ms - -55 -25 - - - - - 1.2 +150 +85 150 A C C C supply voltage flyback supply voltage average quiescent supply current average quiescent flyback supply current total power dissipation during scan during scan 7.5 - - - - - 12 10 - - 1000 - 18 66 15 10 8 V V mA mA W 2 x VP 45 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs and outputs input voltage (peak-to-peak value) output current (peak-to-peak value) 1500 2.0 mV A
Thermal data; in accordance with IEC 60747-1 storage temperature ambient temperature junction temperature
ORDERING INFORMATION TYPE NUMBER TDA8357J PACKAGE NAME DBS9P DESCRIPTION plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad VERSION SOT523-1
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
BLOCK DIAGRAM
GUARD VP VFB
TDA8357J
handbook, full pagewidth
8 GUARD CIRCUIT
3
6
M5 D3 M2
D2
Vi(p-p) D1 VI(bias) 0 INPUT AND FEEDBACK CIRCUIT INB 2 M1 4 M3 OUTB 9 FEEDB INA 1 M4 7 OUTA
Vi(p-p) VI(bias) 0
TDA8357J
5
MGS803
GND
Fig.1 Block diagram.
PINNING SYMBOL INA INB VP OUTB GND VFB OUTA GUARD FEEDB PIN 1 2 3 4 5 6 7 8 9 input A input B supply voltage output B ground flyback supply voltage output A guard output feedback input DESCRIPTION
handbook, halfpage
INA INB VP OUTB GND VFB OUTA GUARD FEEDB
1 2 3 4 5 6 7 8 9
MGS804
TDA8357J
The exposed die pad is connected to pin GND.
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
FUNCTIONAL DESCRIPTION Vertical output stage The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to TV signal processors delivering a differential signal but it is also suitable for single-ended applications. For processors delivering output currents, these currents are converted to voltages by the conversion resistors RCV1 and RCV2 connected to pins INA and INB (see Fig.3). The differential input voltage is compared with the voltage across the measuring resistor RM, providing feedback information. The voltage across RM is proportional to the output current. The relationship between the differential input voltage and the output current is defined by Vi(dif)(p-p) = Io(p-p) x RM and Vi(dif)(p-p) = VINA - VINB. The output current should not exceed 2.0 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bonding wire resistances. Depending on the values of RM and the internal bonding wire resistance (typical value of 50 m) the actual value of the current in the deflection coil will be about 5% lower than calculated. Flyback supply The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows the use of an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/s. Protection The output circuit contains protection circuits for: * Too high die temperature * Overvoltage of output A. Guard circuit
TDA8357J
A guard circuit with output pin GUARD is provided. The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: * During thermal protection (Tj 170 C) * During an open-loop condition. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. Damping resistor compensation HF loop stability is achieved by connecting a damping resistor RD1 across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan. The difference in the damping resistor current values during scan and flyback have to be compensated externally in order to achieve a short settling time. For that purpose a compensation resistor RCMP in series with a zener diode is connected between pins OUTA and INA (see Fig.4). The zener diode voltage value should be equal to VP. The value of RCMP is calculated by ( V FB - V loss ( FB ) - V Z ) x R D1 x R CV1 R CMP = ----------------------------------------------------------------------------------------------------------( V FB - V loss ( FB ) - I coil ( peak ) x R coil ) x R M where: * Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback * Rcoil is the deflection coil resistance * VZ is the voltage of zener diode D5.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP VFB Vn supply voltage flyback supply voltage DC voltage pin OUTA pin OUTB pins INA, INB, GUARD and FEEDB In DC current pins OUTA and OUTB pins INA, INB, GUARD and FEEDB Ilu latch-up current current into any pin current out of any pin Ves Ptot Tstg Tamb Tj Notes 1. When the voltage at pin OUTA is more than 70 V the circuit will limit the voltage. 2. Equivalent to 200 pF capacitance discharge through a 0 resistor. 3. Equivalent to 100 pF capacitance discharge through a 1.5 k resistor. 4. Internally limited by thermal protection at Tj 170 C. THERMAL CHARACTERISTICS In accordance with IEC 60747-1. SYMBOL Rth(j-c) Rth(j-a) PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient in free air CONDITIONS electrostatic handling voltage total power dissipation storage temperature ambient temperature junction temperature note 4 at Tj(max) pin voltage = 1.5 x VP pin voltage = -1.5 x VP machine model; note 2 human body model; note 3 - -200 -350 - -55 -25 - during scan (peak-to-peak value) at flyback (peak); t 1.5 ms - - -20 note 1 - - -0.5 PARAMETER CONDITIONS MIN. - -
TDA8357J
MAX. 18 68 68 VP VP 2.0 1.2 +20 +200 - +350 8 +150 +85 150
UNIT V V V V V A A mA mA mA V W C C C
-4000 +4000 V
VALUE 6 65
UNIT K/W K/W
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
TDA8357J
CHARACTERISTICS VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL Supplies VP VFB IP(q)(av) IP(q) IFB(q)(av) operating supply voltage flyback supply voltage average quiescent supply current quiescent supply current average quiescent flyback supply current note 1 during scan no signal; no load during scan 7.5 2 x VP - - - 12 45 10 30 - 18 66 15 65 10 V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs INA and INB Vi(p-p) VI(bias) II(bias) Vloss(1) input voltage (peak-to-peak value) input bias voltage input bias current note 2 note 2 source current - 100 - 1000 880 25 1500 1600 35 mV mV A
Outputs OUTA and OUTB voltage loss first scan part note 3 Io = 0.7 A Io = 1.0 A Vloss(2) voltage loss second scan part note 4 Io = -0.7 A Io = -1.0 A Io(p-p) LE output current (peak-to-peak value) linearity error Io(p-p) = 2.0 A; notes 5 and 6 adjacent blocks non adjacent blocks Voffset offset voltage across RM Vi(dif) = 0 V VI(bias) = 200 mV VI(bias) = 1 V Voffset(T) VO Gv(ol) f-3dB(h) Gv Gv(T) PSRR offset voltage across RM; variation with temperature DC output voltage open-loop voltage gain high -3 dB cut-off frequency voltage gain voltage gain variation with temperature power supply rejection ratio note 10 Vi(dif) = 0 V Vi(dif) = 0 V notes 7 and 8 open loop note 9 - - - - - - - - 80 - - - 15 25 40 mV mV V/K V dB kHz K-1 dB - - 1 1 2 3 % % - - - - - - 2.8 4.0 2.0 V V A - - - - 3.9 5.5 V V
0.5 x VP - 60 1 1 - 90 - - - 10-4 -
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
SYMBOL Flyback switch Io(peak) Vloss(FB) maximum (peak) output current voltage loss at flyback t 1.5 ms note 11 Io = 0.7 A Io = 1.0 A Guard circuit VO(grd) guard output voltage IO(grd) = 100 A maximum leakage current IL(max) = 10 A VO(grd) = 0 V; not active VO(grd) = 4.5 V; active Notes 5 - - 1 6 - - - - - 7.5 8 - - PARAMETER CONDITIONS MIN. TYP.
TDA8357J
MAX. 1.2 8.5 9
UNIT
A V V
7 18 10 2.5
V V A mA
VO(grd)(max) allowable guard voltage IO(grd) output current
1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA and VFB at the first part of the flyback. 2. Allowable input range: VI(bias) + Vi < 1600 mV and VI(bias) - Vi > 100 mV for each input. 3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and between pins OUTB and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(1) is a positive value. 4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and between pins OUTA and GND. Specified for Tj = 125 C. The temperature coefficient for Vloss(2) is a positive value. 5. The linearity error is measured for a linear input signal without S-correction and is based on the `on-screen' measurement principle. This method is defined as follows. The output signal is divided into 22 successive equal time blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across RM, starting at k = 2 and ending at k = 21, where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum, maximum and average voltages respectively. The linearity errors are defined as Vk - Vk + 1 a) LE = ------------------------- (adjacent blocks) V avg V max - V min b) LE = ------------------------------ (non adjacent blocks) V avg 6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage dependent S-distortion in the input stage. 7. V OUTA - V OUTB G v ( ol ) = ------------------------------------------V FEEDB - V OUTB
8. Pin FEEDB not connected. 9. V FEEDB - V OUTB G v = ------------------------------------------V INA - V INB
10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM. 11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
APPLICATION INFORMATION
TDA8357J
handbook, full pagewidth
VP RGRD 4.7 k GUARD 8 GUARD CIRCUIT D3 VP 3 VFB 6 VFB C1 100 nF C2 100 nF
M5
Vi(p-p) VI(bias)
D2
M2 0 I I(bias) INA 1 RCV1 2.2 k (1%) I i(dif) I I(bias) INB 2 RCV2 2.2 k (1%) Vi(p-p) M4 INPUT AND FEEDBACK CIRCUIT M1 4 M3 OUTB 9 FEEDB RS 2.7 k CM 10 nF RM 0.8 D1 7 OUTA RL 5.2
TDA8357J
VI(bias) 0 5 GND
MGS806
Fig.3 Test diagram.
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book, full pagewidth
2002 May 06
RGRD 12 k GUARD 8 GUARD CIRCUIT 3 Vi(p-p) VI(bias) 0 D1 INA 1 C6 2.2 nF TV SIGNAL PROCESSOR RCV1 2.2 k (1%)
Philips Semiconductors
Full bridge vertical deflection output circuit in LVDMOS
VP = 12 V VFB = 29 V VP VFB 6 C3 100 nF D2 D5 12 V RCMP 270 k 7 OUTA M4 INPUT AND FEEDBACK CIRCUIT M1 4 M3 OUTB 9 FEEDB RS 2.7 k RD1 330 deflection coil 8.82 mH 7.9 (W66ESF) RM 1.5 C1 47 F (100 V) C4 100 nF C2 220 F (25 V)
M5 D3 M2
CD 47 nF RD2 1.5
9
VI(bias) 0
INB 2 C7 2.2 nF Vi(p-p) RCV2 2.2 k (1%)
TDA8357J
5 GND
MGS807
Product specification
TDA8357J
fvert = 50 Hz; tFB = 640 s; II(bias) = 400 A; Ii(p-p) = 475 A; Io(p-p) = 1.4 A.
Fig.4 Application diagram.
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
RM calculation Before calculating the measuring resistor (RM), the differential input voltage [Vi(dif)] has to be known. This voltage can be measured between pins INA and INB. The V i(dif)(p-p) calculation is R M = --------------------I o(p-p) Most of the TV signal processors from Philips have a current output. This current has to be converted by resistors at the input of the TDA8357J (RCV1 and RCV2). The voltage across these resistors can be calculated. The differential input voltage is given in the following equation (refer also to Fig 5): Vi(dif)(p-p) = Ii1(p-p) x RCV1 - (-Ii2(p-p)) x RCV2
TDA8357J
known. These parameters are the required maximum (peak) deflection coil current Icoil(peak), the coil parameters Rcoil and Lcoil, and the measuring resistance of RM. The required maximum (peak) deflection coil current should also include the overscan. The deflection coil resistance has to be multiplied by a factor of 1.2 in order to take account of hot conditions. Chapter "Characteristics" supplies values for the voltage losses of the vertical output stage. For the first part of the scan the voltage loss is given by Vloss(1). For the second part of the scan the voltage loss is given by Vloss(2). The voltage drop across the deflection coil during scan is determined by the coil impedance. For the first part of the scan the inductive contribution and the ohmic contribution to the total coil voltage drop are of opposite sign, while for the second part of the scan the inductive part and the ohmic part have the same sign. For the vertical frequency the maximum frequency occurring must be applied to the calculations. The required power supply voltage VP for the first part of the scan is given by
Ii1(p-p) II(bias) 0
INA C6 2.2 nF TV SIGNAL PROCESSOR RCV1 2.2 k
1
V P ( 1 ) = I coil ( peak ) x ( R coil + R M ) - L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 1 ) The required power supply voltage VP for the second part of the scan is given by
INB C7 2.2 nF RCV2 2.2 k
2
V P ( 2 ) = I coil ( peak ) x ( R coil + R M ) + L coil x 2I coil ( peak ) x f vert ( max ) + V loss ( 2 ) The minimum required supply voltage VP shall be the highest of the two values VP(1) and VP(2). Spread in supply voltage and component values also has to be taken into account. Flyback supply voltage calculation
Ii2(p-p) II(bias) 0
MBL528
Fig.5 Differential input voltage.
If the flyback time is known, the required flyback supply voltage can be calculated by the simplified formula R coil + R M V FB = I coil ( p -p ) x -------------------------- t FB x 1-e where L coil x = -------------------------R coil + R M The flyback supply voltage calculated this way is about 5% to 10% higher than required.
Values for these currents are, for instance Ii(bias) = 400 A; Ii1(p-p) = Ii2(p-p) = 475 A. Therefore the differential input voltage Vi(dif)(p-p) will be 475 A x 2.2 k - (-475 A x 2.2 k) = 2.1 V Supply voltage calculation Before calculating the minimum required supply voltage, several specific application parameter values have to be 2002 May 06 10
Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
Calculation of the power dissipation of the vertical output stage The IC total power dissipation is given by the formula Ptot = Psup - PL The power to be supplied is given by the formula I coil ( peak P sup = V P x -----------------------) + ( V P x 0.015 [A]) + 0.3 [W] 2 In this formula 0.3 [W] represents the average value of the losses in the flyback supply. The average external load power dissipation in the deflection coil and the measuring resistor is given by the formula ( I coil ( peak ) ) P L = ------------------------------- x ( R coil + R M ) 3 Example Table 1 Application values VALUE 0.725 1.45 8.82 7.9 1.5 50 640 Calculated values VALUE 11 11 0.02 0.000802 29 4.45 1.93 2.52 UNIT V s V W W W UNIT A A mH Hz s
2
TDA8357J
Heatsink calculation The value of the heatsink can be calculated in a standard way with a method based on average temperatures. The required thermal resistance of the heatsink is determined by the maximum die temperature of 150 C. In general we recommend to design for an average die temperature not exceeding 130 C. EXAMPLE Measured or given values: Ptot = 3 W; Tamb = 40 C; Tj = 110 C; Rth(j-c) = 6 K/W; Rth(c-h) = 2 K/W. The required heatsink thermal resistance is given by T j - T amb R th ( h - a ) = ----------------------- - ( R th ( j - c ) + R th ( c - h ) ) P tot When specific values are included, this becomes 110 - 40 R th ( h - a ) = --------------------- - ( 6 + 2 ) = 15 K/W 3.0 The heatsink temperature will be Th = Tamb + (Rth(h-a) x Ptot) = 40 + (3 x 15) = 85 C
SYMBOL Icoil(peak) Icoil(p-p) Lcoil Rcoil RM fvert tFB Table 2
SYMBOL VP RM + Rcoil (hot) tvert x VFB Psup PL Ptot
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
INTERNAL PIN CONFIGURATION PIN 1 SYMBOL INA
300
TDA8357J
EQUIVALENT CIRCUIT
1
MBL100
2
INB
300
2
MBL102
3 4 5 6 7
VP OUTB GND VFB OUTA
6
3
7
4
MGS805
5
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
PIN 8 SYMBOL GUARD
300 8
TDA8357J
EQUIVALENT CIRCUIT
MBL103
9
FEEDB
300
9
MBL101
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
PACKAGE OUTLINE
TDA8357J
DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad
SOT523-1
non-concave x Eh
q1
Dh D D1 P k view B: mounting base side A2 q2
E
B
q
L2 L
L3
L1
1 Z e DIMENSIONS (mm are the original dimensions) UNIT A2(2) bp mm c D(1) D1(2) Dh E(1) Eh e e1
9 wM 0 5 scale e1 e2 k L L1 L2 L3 4.5 3.7 m 2.8 P Q q q1 q2 v 0.8 w x Z(1) 1.65 1.10 10 mm Q m e2 c vM
bp
2.7 0.80 0.58 13.2 2.3 0.65 0.48 12.8
6.2 14.7 3.0 12.4 11.4 6.7 3.5 3.5 2.54 1.27 5.08 5.8 14.3 2.0 11.0 10.0 5.5
3.4 1.15 17.5 4.85 3.8 3.1 0.85 16.3 3.6
0.3 0.02
Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Plastic surface within circle area D1 may protrude 0.04 mm maximum. OUTLINE VERSION SOT523-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-11-12 00-07-03
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA8357J
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. suitable suitable(1) WAVE
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
DATA SHEET STATUS DATA SHEET STATUS Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA8357J
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
NOTES
TDA8357J
2002 May 06
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
NOTES
TDA8357J
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Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit in LVDMOS
NOTES
TDA8357J
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/03/pp20
Date of release: 2002
May 06
Document order number:
9397 750 09637

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